1. Field of the Invention
The present invention relates to a method for selecting a sequence of cells of current sources inside a cell matrix structure of a digital-analog converter.
2. Background of the Invention
There is a need for fast and accurate digital-analog converters, for instance in high-definition video systems.
Known digital-analog, or D/A, converters are based on matrixes of cells of current sources and for instance of CMOS sources. Usually each cell corresponds to a current source and the final output from a D/A converter is obtained by summing the respective outputs of the current sources selectively addressed. The current sources to be switched on are selected on the basis of an inputted digital value and according to a method chosen for providing a high level of linearity to the D/A converter.
As pointed out for instance in an article entitled "A 10-b 70-MS/s CMOS D/A Converter" published in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 26, N.sup.o 4, APRIL 1991, pages 637-642 by Yasuyuki NAKAMURA & al, an integral linearity error is caused by error distribution of current sources and a method for reducing such an error is based on so-called "hierarchical symmetrical switching". As mentioned in the above cited article, graded errors are induced by voltage drops along the power supply lines of the sources in a D/A converter chip and symmetrical errors are induced by thermal distribution inside the chip.
The hierarchical symmetrical switching foreseen in the cited article, is based on a selection of sources row by row according to the analog value to be outputted and symmetrically for a given row with regard to the middle of this given row. However if a mismatching compensation is obtained for the sources according to the rows of a matrix, there is no compensation of symmetrical errors foreseen for the sources according to the columns.
Using hierarchical symmetrical switching in two dimensions instead of one is foreseeable. however a straightforward implementation of it results in a complex decoding logic associated with a complex routing and consequently to an oversized matrix area. Furthermore there is a degradation of the converting speed when compared with the speed of an arrangement in one dimension as foreseen above.